In a conventional design methodology for a programmable platform device (e.g., platform and structured application specific integrated circuits (ASICs)), a developer assigns up to 256 Low Pin Count (LPC) pins for each slice. Each of the pins of a slice are categorized as No Test, Dedicated, Shared, or Reserved. If a pin is marked as Dedicated, Shared, or Reserved, the pin is considered a LPC pin.
The conventional methodology can be too restrictive. With the conventional methodology, scan pins are fixed and there are certain classifications of buffers that cannot be used for test sharing. For example, if a layout includes a 32 bit stub series termination logic (SSTL) bus, the probability is quite high that a pin to be used will be marked as a test_share pin. However, SSTL buffers cannot be used with test_share pins.
The conventional solution involves the manufacturer manually changing the limited amount of test pins. The process is manual, error prone, and time consuming. In addition, changes can only be performed by the manufacturer. Therefore, a vendor must rely on the manufacturer to make the changes. Only non-scan pins are allowed to change with the current methodology.
It would be desirable to have a method and/or tool for automatic test pin assignment.